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You need to make clock dividers to get lower frequencies.
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If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable. You said you are using a schematic. Choose register primitives that show the clock enable port. Some megafunctions also have a clock enable port available; it might be an option you have to select.
If you drive a lower-speed clock directly from the divide-by-2 register instead of using a clock enable, then it would be best not to have any synchronous paths crossing to or from the divided-down clock domain. In other words, set up the design so that the timing on cross-domain paths does not matter, and use cut-path (false-path) settings to tell Quartus to ignore the timing on the cross-domain paths. (There's also a way to do it with clock settings.) That way the clock skew won't matter for paths that cross between clock domains. Also make sure the divided-down clock is on a global line (you can force this in the Assignment Editor if the Fitter doesn't make the clock global automatically) to minimize clock skew between registers within the domain.
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