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If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable.
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Could you explain it in detail ?
Now I am using a PLL in my project to generate a global clock(clk). The frequency of clk is beyond my need. What should to do ?
Divide clk to the new one I need, or change the PLL to a divider to generate my needed clock ?
Thanks.
hapyang
Honored Contributor
