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If you do divide the higher-speed clock with a register, it would be better to create a clock enable with the divided-down signal instead of driving a lower-speed clock directly from the divide-down register. For example, use the PLL to create a clock that is twice as fast as the needed frequency, then use a divide-by-2 signal as a clock enable. You said you are using a schematic. Choose register primitives that show the clock enable port. Some megafunctions also have a clock enable port available; it might be an option you have to select.
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The only megafunction that I could find that had a clock enable was LPM_FF. I'm not sure if this is what you were refering to or not?
Also, I'm using the Cyclone II FPGA.
Thanks.
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