Occasional Contributor
Super ContributorI'm running out of ideas. Can you break down these components into multiple subsystems, leaving the top basically empty except for subsystem instantiations and connections?
I don't know how complex this custom component is but it is clearly the cause of the problem. How many parameters are there?
Occasional ContributorThe top level system only includes subsystems and some components (e.g. PCIe HIP, some register). It instantiates one larger subsystem, that also contains some components (e.g. Avalon-MM bridge), but also 2 instances of one subsystem. These two subsystems contain the ~60 custom generic components - so ~30 for each. I tried to show the basic hierarchy in the image below:
The top level qsys doesn't contain anything but instantiations and connections or do I misundertsand you?
As mentioned above the custom generic component has 25 parameters but 16 of them are derived and set during the elaboration callback. Some of these parameter salso define the port widths of interfaces and one chooses the FIFO. The elaboration callback function is about 100 LoC in the hw.tcl file. The VHDL code of the custom generic component is ~700 LoC, but the VHDL shouldn't be analyzed when opening the top level qsys file anyway or is it?
Best Regards,
Florian
Super ContributorYes, the code is analyzed when opening the system to make sure everything will work in PD.
With these details, this is a very large complicated system. I am now not really surprised at the issue you are seeing.
Are all 60 generic components completely unique as far as parameters? Is there no way to make any of them fixed component designs?
Occasional ContributorThere is one parameter, that chooses which FIFO is instantiated within the component. This parameter also defines most of the port's widths by setting other parameters. There are 5 different values for this parameter.
Four parameters are often shared between the instances of the custom component. These are only used in the VHDL code and do not define any port width.
Two parameters are completely unique for each instance, but are also only used in the VHDL code and do not define any interface.
One parameter is completely unique for each instance and also defines the width of a port. But the port belongs to a dummy interface that is necessary due to the problem described here: Problem with parameters when instantiating custom build component - Intel Community
All the other parameters are derived and depend on the first parameter mentioned (FIFO type) and are either used in the VHDL code or within the hw.tcl file to define port widths.
The only parameter that is not necessary is the last one mentioned, but without it the error described in the other thread appears.
I had also, as mentioned in a previous reply, tried to remove most of the parameters from the component and that didn't improve the performance.
