Platform designer very slow when opening top level system (21.1 Std)

So far none of the (sub-)systems seems to be corrupted. When recreating the subsystems and instantiating them in the top level the platform designer starts to get really slow. So slow that for adding a single connection on top level it takes minutes if not an hour.

Can the file size per se be a problem? The top level .qsys has about 180 kB in size and the subsystems range from 10 to 90 kB. The one that has 90 kB e.g. is instantiated two times in the whole design.

Are generic components a problem? As mentioned above I instantiate the same generic component about 60 times in the whole design with different parameters. Depending on the parameters set the component chooses which FIFO to instantiate in its VHDL code (it chooses 1 of 5 FIFO). The 5 FIFO are referenced in the hw.tcl of the component and are instantiated in the VHDL code via a "if .. generate" depending on the parameter set.

Or can elaboration callback functions cause the problem? This generic component's hw.tcl also includes an elaboration callback of about 100 lines in code. Bit I had tried to "simplify" the component by splitting it up in multiple "pre defined" components with little to no parameters and lines in the callback function and the performance didn't improve.

Best Regards,
Florian