Forum Discussion
Vicky1
Regular Contributor
7 years agoHi ESher1,
Yes, document differ from reality.
I confirmed that, since the Intel Quartus v15.0 , the Modelsim-Intel FPGA edition software supports dual/mixed language simulation.
It will generate simulation model for top level module as per the specified HDL language but not the interconnect, in this case(VHDL), you may use the simulator which supports only single language.
Refer the link below for ModelSim-Intel FPGA edition software especially for 'Frequently Asked Questions',
https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html
Regards,
Vikas