Platform designer needs ModelSim PE mixed language license?

​The document you posted is highly misleading as the options it describes are not available in Platform Designer. Specifically the option "Allow mixed-language simulation" does not exist, so the first statement under Simulating a Qsys System "Generate the Verilog HDL, VHDL, or mixed-language simulation model for your system to use in your own simulation environment." is also incorrect because without this option it cannot generate a VHDL only simulation model, only a mixed-language simulation.

I currently have a number of ModelSim PE/VHDL licenses, these were purchased in preference to ModelSim-Altera because PE offers higher simulation speeds and is compatible with other vendor's tool chains. I do not write any Verilog code, nor do I need to maintain any, so there is no other reason for me to need Verilog support in ModelSim PE. The removal of the option to turn off "allow mixed language simulation" would force me to upgrade all of my ModelSim PE/VHDL license to ModelSim PE/Plus to maintain the same simulation performance as I currently enjoy with 13.1. I would be forced into this upgrade purely to simulate Platform Designer systems.

Can you confirm that there is no way to turn off "Allow Mixed-language Simulation" in 18.x's Platform Designer. Or has this very useful feature been removed permanently? Why does it not clearly state in the Platform Designer documentation that it is not compatible with single language HDL simulators?