Occasional ContributorPCIe HIP clocking regression on Stratix 10 MX in Quartus Prime Pro 22.2
I just installed Quartus Prime Pro 22.2 (upgrading from 21.3) and I have run in to a strange issue with the H-tile PCIe IP core. I have the core configured for 512 bits and 16 lanes.
In 21.3, all of the clocks are listed correctly in the timing report. Under "setup summary", there are 5 clocks listed.
In 22.2, all of the PCIe clocks are missing from the timing report, with only 3 clocks listed under "setup summary". Interestingly, they are listed in the "clocks" section, but the frequency of the three HIP iopll outputs are incorrect (10/1/1 ns instead of 40/4/4 ns). Another oddity is that there are also no unconstrained paths. I tried recreating the IP core from scratch and rebuilding, but the result was the same, so this seems to be some sort of issue within Quartus itself.
I am currently downloading 21.4 and 22.1 to try to isolate what version of Quartus introduced this regression.
Clocks listed in 21.3 under "setup summary":
- pcie_hip_inst|pcie_s10_hip_ast_0|altera_avst512_iopll|altera_ep_g3x16_avst512_io_pll_s10_outclk0
- pcie_hip_inst|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x16.phy_g3x16|phy_g3x16|xcvr_hip_native|ch0
- altera_int_osc_clk
- ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk
- clk_sys_100m
Clocks listed in 22.2 under "setup summary":
- altera_int_osc_clk
- ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk
- clk_sys_100m
Has anyone else run in to this issue? Are there any known workarounds?
Edit: it appears that the 256 bit, 8 lane version is also affected, with the missing clock being pcie_hip_inst|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0.
