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alexforencich's avatar
alexforencich
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

PCIe HIP clocking regression on Stratix 10 MX in Quartus Prime Pro 22.2

I just installed Quartus Prime Pro 22.2 (upgrading from 21.3) and I have run in to a strange issue with the H-tile PCIe IP core. I have the core configured for 512 bits and 16 lanes. In 21.3, all ...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Alex,

I am trying to reproduce the PCIe AVST example design in Quartus.
It might take sometime due to limited bandwidth that I have, get back to you soon as possible

Apologize for the inconvenience caused.

Regards,

Wincent_C_Intel

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Alex,

    I successfully replicate your error on my side, I had escalated this to the engineering team.
    I will keep this loop open, It might take some time for them to investigate the issue.

    Will update here soon as possible once i get their feedback.


    Regards,

    Wincent_C_Intel