PCIe HIP clocking regression on Stratix 10 MX in Quartus Prime Pro 22.2

1. I wasn't referencing a user guide, I just deleted the core and created a new one from the IP library, configuring the appropriate settings in the parameter editor. Originally, the core was created via TCL, which was exported from the parameter editor in a previous version of Quartus. I recreated it manually to rule out any issues in the exported TCL.
2. It's the AVST core
3. I suspect that the issue will appear in the AVST example design. But, I just did some quick testing, and it's also a problem on the 8 lane, 256 bit configuration of the same core, and that design is available here: https://github.com/corundum/corundum/tree/master/fpga/mqnic/S10MX_DK/fpga_10g

Edit: Actually, this design is simpler, and exhibits the same problem: https://github.com/alexforencich/verilog-pcie/tree/master/example/S10MX_DK/fpga