Hi, I'm a C programmer which is suppose to learn VHDL in 21 days;p. We're developing a device which is connected to 32 bit Atom processor with PCIExpress bus. We have Altera Aria II Gx FPGA. The device must do very data operation on 256bits of data. Then it should return it back to the Atom. For the device driver purposes I also need status register, and same configuration registers, which can be even bigger then 2kB. So my question is which components should i use to not make my boss upset;). What I've done before writing this post, is communication with internal dual port ram with use of DMA. It's all been done by SOBC. I can read data written to this memory on the port B. I wan't to read this data as soon as it's possible, and i'm thinking of copying address from port A to port B and make a process be sensitive on WENA signal, so I would read it just after it's written. I'm thinking of making clk_b <= not clk_a; so I'll be able to read data a half clock period after it's written, and write data back to port B being sure that there's nothing to read at the moment ( ADDR_B <= ADDR_A when not WENB else ADDR_PROCESSED_DATA; WENB <= not WEN_A and not CS_A and HAVE_SOMETHING_TO_WRITE; CLK_B <= not CLK_A; What do You think? Thank You very much for any suggestions.

Ok, let's simplify it. Let's say You want to send a packet containing 128 bits trough PCIe, do some calculations on it, and then send it back to microprocessor trough PCIe. Which components will You use? OnChipMemory? DMA? FIFO?

I can't believe it! No one answers to this question. Why? Is it to complicated, wrong forum?

Your ideas sound fine to me. Why not just go ahead and implement them? I looked at the Altera PCIe core and wrote up some notes: http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip I wasn't particularly impressed with the Qsys component. It should really have a DMA bridge as part of the component. For your design, I'd generally use two clocks; PCIe clock and FPGA clock. I'd then use a dual-clock FIFO to cross clock domains. This allows you to have the data processing clock (the FPGA clock) faster than the PCIe clock (if you want). Cheers, Dave

First I'd get it all working using PIO transfers from the atom and software polling for completion. You'll probably need that access to debug it all anyway - being able to hexdump on-chip memory/register areas is very useful. You can then work on getting the fpga's PCIe master interface, and then dma to read/write host memory. And also getting a 'completion' interrupt working. If you are using a nios you should find it fairly simple to download code from the host (atom), that will be more productive than using JTAG. But I agree with dwh, the pcie block ought to contain a simple dma transfer engine (feed avalon address, pcie address, count and press 'go').

I followed Your suggestions and try to create a cross clock domain using small fifo. And now I'm facing a problem with catching pio value. Let's assume i have 4 pio 32 input ports, and 4 pio output ports. All PIO ports are mapped in memory, and were connected to two 128bit signals, which I tought were holding the real state of the port, and they did so, before i connected the 128 bit signal to the cross_clock_fifo. After i connected the fifo all i see in memory is 0xffffffff. I figure out, that there's no D flipflop - so the data couldn't be catched nowhere. I added then a process which i thought would catch data at 128 bit port. But it isn't. It works only for the first write to the memory. After second write all i read is 0xfffffff. How can I make this data be available at the memory, and also pass it to the cross_clock_fifo? changing '0'->'1' at enc_in_ctrl_write=>in_port_to_the_pio_enc_in_ctrl(0) should add pio datas to fifo.

PC Device communication howto | Altera Community

18 Replies

Altera_Forum
Honored Contributor
13 years ago
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Your tutorial is great:D

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Thanks! I'm glad you found it useful.

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I've another question, how can i add to this tutorial a top file (without SOPC), where i implement my logic which would for ex copy data from button to led using fifo. I want to be able to define a FSM which I'll be able to debug in simulator.
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If you don't want that logic to interact with the Qsys/SOPC system, you just 'steal' the pins, eg., disconnect the buttons and LEDs from the Qsys connections, and run them to your circuit.

However, you now have a JTAG connection to your FPGA that you can read and write registers with. There really is no point in using LEDs and push-buttons to do things, i.e., manual operation of the hardware.

You can manually call a software procedure much easier, and then when you want to run the test 1k times, you won't get a sore finger or get bored :)

Think about what you are really trying to achieve and see if a software approach will work better for you.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
OK. As i mentioned i want to learn a bit, and want to connect Your button and led through fifo. I added FSN a nearby the end of sopc_system.v and using Megawizard added a small fifo. But when I try to run simulation i get error:** Error: (vsim-3033) ../sopc_system.v(4691): Instantiation of 'cross_clk' failed. The design unit was not found. I have no idea how am i suppose to add file cross_clk.v to simulation library. Thanks
Altera_Forum
Honored Contributor
13 years ago
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I added FSN a nearby the end of sopc_system.v
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This is a *generated* file. To add to this file you should create an SOPC component and add it via the GUI, otherwise your edits will be erased when you 'regenerate' the SOPC System.

As I commented above, if you want to add a component that has nothing to do with the SOPC system, add it to the top-level design file.

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But when I try to run simulation i get error:** Error: (vsim-3033) ../sopc_system.v(4691): Instantiation of 'cross_clk' failed. The design unit was not found. I have no idea how am i suppose to add file cross_clk.v to simulation library.
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Look at the scripts synth.tcl and sim.tcl. These scripts contain the commands to include the source files for Quartus and Modelsim. If you change the HDL, then edit these scripts to add your new files to the list.

Let me know if you need more detailed instructions.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Modelsim is great, and saves me a lot of time. But now i have to figure out how can I include a vhdl library to the tesbench. I know that code mixing is now available in altera modelsim, is there any workaround to do it? Build a library, convert vhdl code to verilog, dowload diffrent simulation tool (trial verision?)? Whatever? Thank You.
Altera_Forum
Honored Contributor
13 years ago
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But now i have to figure out how can I include a vhdl library to the tesbench. I know that code mixing is now available in altera modelsim

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Do you mean "not available"?

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is there any workaround to do it? Build a library, convert vhdl code to verilog, dowload diffrent simulation tool (trial verision?)? Whatever? Thank You.
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No, not really. You can synthesize a design and output a .vo or .vhd file, but they you lose the ability to probe the internal signals.

I use Modelsim-SE (full version) for my mixed language designs.

When creating tutorials to be run in Modelsim-ASE I write the code as fully SystemVerilog or fully VHDL.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
Yes i ment "not available". What a pity! Mayby You have, or anybody else a modelsim project created for VHDL?
Altera_Forum
Honored Contributor
13 years ago
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Yes i ment "not available". What a pity! Mayby You have, or anybody else a modelsim project created for VHDL?
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The problem is that Altera does not supply the required IP in VHDL format. If you want to use Modelsim-ASE and want to use Altera IP that is in Verilog or SystemVerilog, then you need to write your code in SystemVerilog too.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I've found a 15-day full trial which converted vhdl to verilog: veritak (http://www.sugawara-systems.com/download.htm)

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