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But now i have to figure out how can I include a vhdl library to the tesbench. I know that code mixing is now available in altera modelsim
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Do you mean "not available"?
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is there any workaround to do it? Build a library, convert vhdl code to verilog, dowload diffrent simulation tool (trial verision?)? Whatever? Thank You.
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No, not really. You can synthesize a design and output a .vo or .vhd file, but they you lose the ability to probe the internal signals.
I use Modelsim-SE (full version) for my mixed language designs.
When creating tutorials to be run in Modelsim-ASE I write the code as fully SystemVerilog or fully VHDL.
Cheers,
Dave
Honored Contributor
