Parameterized interface modports question

Hi,

I've recently started using SystemVerilog and I wish to use a generic memory interface in some of my modules, in order not to tie their use to a given particular memory or system bus, in a way that I could simply bind adapters to the top of the module hierarchy and let it roll with whatever memory/bus interfaces I wish, with little extra effort.

But the interface is parameterized and contains two modports, as such:

interface GenericMemPort# (parameter int ADDR_WIDTH, DATA_WIDTH);
    logic  addr;
    logic  data;
    logic write, read;
    logic ack;
    
    modport host (input addr, inout data, input write, input read, output ack);
    modport client (output addr, inout data, output write, output read, input ack);
endinterface

Although my particular module hierarchy has tight restrictions as to what size is the address and data bus widths, I would like to keep the interface like that for use in other module hierarchies.

But to do that, I don't understand which syntax to use when using these modports inside modules. How do I define their parameters?

module Raster# (
    parameter int MEM_ADDR_WIDTH = 24 // memory interface address width
)
(
    // clock and reset signals
    input clk,
    input rst,
    
    // memory interface
    ArbiterPort.client
   # (
        .ADDR_WIDTH (MEM_ADDR_WIDTH), // although address width may vary ...
        .DATA_WIDTH (32) // data width HAS to be 32 for this module to work
    ) memory
);
// <todo> module body goes here
endinterface

This doesn't seem to work, and I have seen people saying doing this is impossible. They say you have to generically define "memory" as "interface.client", for example, and set the parameters externally, by first instantiating the interface and tying it to the correct port. But this is a problem, since the module has actual restrictions as to what the data width has to be.

What should I do?