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Altera_Forum's avatar
Altera_Forum
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16 years ago

Parameterized interface modports question

Hi, I've recently started using SystemVerilog and I wish to use a generic memory interface in some of my modules, in order not to tie their use to a given particular memory or system bus, in a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yeap, AFAIK it is not possible to do like you want.

What seams to be possible is to add an assertion inside the module to test that the address width is 32 and through an error if it doesn't.

But there is a bug in Quartus (acknowledged in version 9.0) that does not let you read the parameters declared in an interface outside of a module :(

Maybe that bug has been fixed in 10.0 ?