Honored Contributor
Honored ContributorI think this is a shame and a language inconsistency (i.e. some language features fail to support or defeat each others' purposes entirely). Should I try VHDL? I just didn't like its syntax much..
In any case, how would you assert an interface parameter value from within a module using it? I thought about using an assert exactly like this, but I thought I should ask other's opinions before, since I've never used assertions and since this particular usage of assertions looks one hell of an ugly hack :p It'd be easier for me if you could give me a few pointers; I'd be very grateful. Thanks, n2
