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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Parameterized interface modports question

Hi, I've recently started using SystemVerilog and I wish to use a generic memory interface in some of my modules, in order not to tie their use to a given particular memory or system bus, in a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I like VHDL better. The only stuff that SystemVerilog has better than VHDL is the interfaces, but interfaces are limited like you have found out. Mentor Graphics (The company behind Modelsim) wrote a white paper complaining that interfaces are actually evil. I would present a link here, but I can not find it right now. Maybe Ben Cohen has it ?

Anyway, inside the module just do: 


initial begin
  // only works in proper simulators
  assert(ArbiterPort.DATA_WIDTH == 32)
  else $fatal(2,"DATA_WIDTH must be 32bits for this module to work");
  // This should make Quartus complain (a.k.a. poor man's assertion )
  if (ArbiterPort.DATA_WIDTH != 32) Call_undef_function();
end