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DavidMapstone's avatar
DavidMapstone
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1 year ago

Output Encrypted Verilog Simulation Netlist with Encrypted Sources

Hi, I am trying to produce a verilog simulation netlist using quartus pro but my design contains encrypted RTL. The netlist is successfully implemented but using the quartus_eda tool, it produces an...
Compilation
Simulation
HubertG's avatar
HubertG
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1 year ago

Hi DavidMapstone,


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.