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Altera_Forum's avatar
Altera_Forum
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11 years ago

Out entity parameter as function argument

Hi!

Let me begin from code example: 


...
entity three is
    port (do3 : out std_logic_vector(2 downto 0));
end entity three;
...
entity Test is
    port (data : out std_logic);
end entity Test;
architecture Test of Test is
    type onetwo_t is record
        one : std_logic;
        two : std_logic_vector(1 downto 0);
    end record;
    function convert (lv : std_logic_vector(2 downto 0)) return onetwo_t is
    begin
        return (one => lv(0), two => lv(2 downto 1));
    end;
    signal onetwo : onetwo_t;
begin
    three : entity work.three
        port map ( convert(do3) => onetwo );
    data <= onetwo.one;
end architecture Test;

So, I want call function convert with out parameter data in left hand side on entity instantiation. In Quartus I got error: 


Error (10344): VHDL expression error at fifo_rl.vhd(198): expression has 2 elements, but must have 3 elements
Error (10344): VHDL expression error at fifo_rl.vhd(198): expression has 3 elements, but must have 2 elements

where fifo_rl.vhd(198) is line with convert function call.

But this code works with ghdl.

So, is it possible to do such function calls?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I think this is a bug with with quartus vhdl compiler, as a colleague just had exactly the same problem. The work around is to use an intermediate signal.

    Raise an issue with quartus mysupport, maybe they'll fix it one day.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You have the following instantiation:

    three : entity work.three

    port map ( convert(do3) => onetwo );

    But you cannot have a function call as a formal in a port map. That is not legal VHDL.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    You have the following instantiation:

    three : entity work.three

    port map ( convert(do3) => onetwo );

    But you cannot have a function call as a formal in a port map. That is not legal VHDL.

    --- Quote End ---

    Wrong, it's perfecctly legal VHDL. You can have a type conversion as long as it has only a single argument on either the LHS or RHS of a port map assignment.