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Altera_Forum
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11 years ago

Out entity parameter as function argument

Hi! Let me begin from code example: ... entity three is port (do3 : out std_logic_vector(2 downto 0)); end entity three; ... entity Test is port (data : out std_logic); end enti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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You have the following instantiation:

three : entity work.three

port map ( convert(do3) => onetwo );

But you cannot have a function call as a formal in a port map. That is not legal VHDL.

--- Quote End ---

Wrong, it's perfecctly legal VHDL. You can have a type conversion as long as it has only a single argument on either the LHS or RHS of a port map assignment.