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Altera_Forum's avatar
Altera_Forum
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16 years ago

open-drain/open collector type of output

Hi All,

This might have been discussed before, but I didn't see a definite answer.

I have one IO pins which I wanna assign it to be a open-drain type. I tried to add the following attribute to the VHDL:

ATTRIBUTE altera_io_opendrain : boolean;

ATTRIBUTE altera_io_opendrain OF timeout: signal is true;

Quartus II 9.0 Web gives me a "Warning (10335): Unrecognized synthesis attribute "altera_io_opendrain" at WATCHDOG/WDT.vhd(24)"

Anyone knows why? More, anyone knows a way to configure an IO pin as open drain type directly?

Thanks

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Open drain is a regular tri-state output, that uses the states '0' and 'Z' only.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Try something like this....

    output_pin <= '0' when (output_signal = '0') else 'Z';
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    altera_io_opendrain is a Synopsys synthesis attribute. It's not used by Quartus at all.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    Open drain is a regular tri-state output, that uses the states '0' and 'Z' only.

    --- Quote End ---

    Actually, most FPGA and CPLD families have a dedicated Open Drain configuration control. See the IOE structure diagram.

    I'm not sure what is the purpose of this Open Drain configuration, when it is not strictly needed. In most cases it won't even save user logic.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The open-drain configuration is required to allow the pin to sink current.

    Actually, Quartus will usually infer a IOE open-drain configuration from the code that gmstr posted.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    The open-drain configuration is required to allow the pin to sink current.

    --- Quote End ---

    Sorry, I don't get why you would need a specific dedicated IOE configuration for that purpose.

    If the data output at the IOE is permanently tied to ground, and the original data signal is negated and then used as Output Enable, then you effectively has an open drain output.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    An open-drain output should be nothing more than a single mosfet with the source connected to the ground. And surely enough, a simple CMOS tri-state gate with D=0 will do just that.

    But, and I'm speculating here, an FPGA IOE with it's many features (programable slew rate, programable current strenght, PCI clamp diode, etc, etc) might, somehow, behave a bit differently and Altera chose to add a bit of extra circuitry to make sure it behaves as expected from an open-drain.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Without knowing the exact transistor circuit of the output driver block, you can only guess about the purpose of a dedicated open drain feature. It could be better switching behaviour. And I imagine, it can be achieved by extending the current strength and impedance control by compeletely disabling the high side output transistors.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I guess that what you both are saying, is very possible. But then I would expect this to be mentioned somewhere in the literature.