Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- Open drain is a regular tri-state output, that uses the states '0' and 'Z' only. --- Quote End --- Actually, most FPGA and CPLD families have a dedicated Open Drain configuration control. See the IOE structure diagram. I'm not sure what is the purpose of this Open Drain configuration, when it is not strictly needed. In most cases it won't even save user logic.