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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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On-chip FIFO aclr signal

It would be helpful if you could teach me about the FIFO provided by IP.

As the title suggests, it would be helpful if you could teach us the following points regarding the behavior when the aclr signal is asserted.

　1) The description in the "FIFO Intel FPGA IP User Guide" says "clear all output status ports". Does this mean that the contents of the memory cells are cleared?

　2) What will be output if reading is performed immediately after aclr is released?

Sorry for the elementary question, but it would be helpful if you could teach me.

that's all

  • Kshitij_Intel's avatar
    Kshitij_Intel
    3 years ago

    Hi,

    The 3 different functionality of aclr in Table 11 is depends on the how you are proccessing the aclr signal, means how the aclr behaves in different scenarios. i.e., when the aclr is depend on the write clock or read clock and when it is not dependent on any read/write clock.

    For Add circuit to synchronize 'aclr' input with 'wrclk' this is an option in FIFO IP Parameter editor. Sharing the screenshot.

    I hope it is clear now.

    Thank you

    Kshitij Goel

6 Replies

    • Yamada1's avatar
      Yamada1
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Thank you for answering.

      I have checked the document, but it would be helpful if you could teach me about the following points.

      "aclr (synchronize with write clock)" and "aclr (synchronize with read clock)" in Table 11 are respectively "Add circuit to synchronize 'aclr' input with 'wrclk'" and "Add circuit to synchronize 'aclr' input with ' Is it correct to understand that it will be referenced when checking "rdclk'"?

      I apologize for the elementary question, but thank you in advance.

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,

    The 3 different functionality of aclr in Table 11 is depends on the how you are proccessing the aclr signal, means how the aclr behaves in different scenarios. i.e., when the aclr is depend on the write clock or read clock and when it is not dependent on any read/write clock.

    For Add circuit to synchronize 'aclr' input with 'wrclk' this is an option in FIFO IP Parameter editor. Sharing the screenshot.

    I hope it is clear now.

    Thank you

    Kshitij Goel

    • Yamada1's avatar
      Yamada1
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Thank you for answering.

      Your explanation with diagrams was very helpful.

      If there is no check mark in the underlined part of the screenshot you provided, is it correct to assume that the "Asynchronous Clear (aclr)" column in the aclr function in Figure 11 applies and does not depend on the read/write clock?

      Sorry for the inconvenience, but thank you in advance.

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you

    Kshitij Goel