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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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On-chip FIFO aclr signal

It would be helpful if you could teach me about the FIFO provided by IP. As the title suggests, it would be helpful if you could teach us the following points regarding the behavior when the aclr s...
  • Kshitij_Intel's avatar
    Kshitij_Intel
    3 years ago

    Hi,

    The 3 different functionality of aclr in Table 11 is depends on the how you are proccessing the aclr signal, means how the aclr behaves in different scenarios. i.e., when the aclr is depend on the write clock or read clock and when it is not dependent on any read/write clock.

    For Add circuit to synchronize 'aclr' input with 'wrclk' this is an option in FIFO IP Parameter editor. Sharing the screenshot.

    I hope it is clear now.

    Thank you

    Kshitij Goel

Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thank you for answering.

I have checked the document, but it would be helpful if you could teach me about the following points.

"aclr (synchronize with write clock)" and "aclr (synchronize with read clock)" in Table 11 are respectively "Add circuit to synchronize 'aclr' input with 'wrclk'" and "Add circuit to synchronize 'aclr' input with ' Is it correct to understand that it will be referenced when checking "rdclk'"?

I apologize for the elementary question, but thank you in advance.