Forum Discussion
Occasional ContributorOn-chip FIFO aclr signal
Hi,
The 3 different functionality of aclr in Table 11 is depends on the how you are proccessing the aclr signal, means how the aclr behaves in different scenarios. i.e., when the aclr is depend on the write clock or read clock and when it is not dependent on any read/write clock.
For Add circuit to synchronize 'aclr' input with 'wrclk' this is an option in FIFO IP Parameter editor. Sharing the screenshot.
I hope it is clear now.
Thank you
Kshitij Goel
Frequent ContributorHi,
The 3 different functionality of aclr in Table 11 is depends on the how you are proccessing the aclr signal, means how the aclr behaves in different scenarios. i.e., when the aclr is depend on the write clock or read clock and when it is not dependent on any read/write clock.
For Add circuit to synchronize 'aclr' input with 'wrclk' this is an option in FIFO IP Parameter editor. Sharing the screenshot.
I hope it is clear now.
Thank you
Kshitij Goel
Yamada1Thank you for answering.
Your explanation with diagrams was very helpful.
If there is no check mark in the underlined part of the screenshot you provided, is it correct to assume that the "Asynchronous Clear (aclr)" column in the aclr function in Figure 11 applies and does not depend on the read/write clock?
Sorry for the inconvenience, but thank you in advance.
