No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus II 7.1 :

From To Assignment Name Value Enabled

CLK_OUT_48 N_SLWR th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[0] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[1] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[2] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[3] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[4] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[5] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[6] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[7] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[8] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[9] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[10] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[11] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[12] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[13] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[14] th Requirement 4 ns Yes

CLK_OUT_48 DATA_OUT[15] th Requirement 4 ns Yes

The nodes were taken from the Node Finder and i have tried both the "post fitting" and "pins" filters. Regardless how i specify the source/destination i end up with the following in the compilation report (under "Ignored Timing Assignments"):

th Requirement 5 ns CLK_OUT_48 DATA_OUT[0] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[10] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[11] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[12] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[13] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[14] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[15] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[1] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[2] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[3] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[4] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[5] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[6] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[7] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[8] No timing path applicable to specified source and destination

th Requirement 5 ns CLK_OUT_48 DATA_OUT[9] No timing path applicable to specified source and destination

th Requirement 4 ns CLK_OUT_48 N_SLWR No timing path applicable to specified source and destination

tsu Requirement 4 ns * CLK_OUT_60 No timing path applicable to specified source and destination

Any help is appreciated.