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Altera_Forum
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18 years ago

No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus I...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Thanks FvM. You are probably correct in that a 4ns programmable delay is not possible to achieve (possibly because i'm not using output registers). The LCELL approach works fine so i'll leave it at that - the clock frequency is only 120 MHz so i have lots of wiggle room before the timings break down so this should work fine.