No timing path applicable to specified source and destination

The point is, that Quartus software has no means to achieve a 4 ns order of magnitude delay in place and route. The said output register to output pin delay should be utilized in timing-driven P&R automaticly, but probably you're not using output registers in your design. Comparing output and LE register usage, LE register would have generally higher tco, cause routíng delay is added. Thus it could be, that Quartus already has achieved the highest possible tco value. Some amount of output delay could be added by decreasing current strength, increasing also sensitivity to parameter variations.