Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

FYI: I gave up on the Quartus II timing assignments and instead inverted the clock signal and followed with four LCELLs. This resulted in my clock aligned perfectly in the middle of my data. I have around 4 ns margin in either direction so i'm 'hoping' that this will work despite variation in delay with different silicon batches...