no setup paths were found in quartus by Report timing

hi,

I am doing the constrains for the 1000 base T1 eth. In the receiving path, FPGA get rx clock and center aligned ddr data. i use the altddrio primitive to capture the ddr data. The fpga is cyclone V.

I create a 90 degree shift virtual clock and set the input delay. By add addtional Programmable IOE Delay D1, the design already worked.

I met several problem by the timing report for the above case:

1. when I try reporting timing for the input signal, i want the check the setup and hold up slack for the altddrio. I get the massage as follow:

It seems there is no register path detected. it happens also for the hold up report. I also set falsh path like this:

2. Because the delay by IOE D1 needs to be added in the project qsf file, I try to set a general constrains that can be reused convenient also by other projects without changing the qsf file. I want to move this delay to the constrain file by the input delay, I increase the input delay based on the following table:

Then the design doesn't work. It this idea correct? If yes, how should I do this?