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Jing_x's avatar
Jing_x
Icon for New Contributor rankNew Contributor
2 years ago

no setup paths were found in quartus by Report timing

hi, I am doing the constrains for the 1000 base T1 eth. In the receiving path, FPGA get rx clock and center aligned ddr data. i use the altddrio primitive to capture the ddr data. The fpga is cyclo...
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


1.You can't find the setup and hold up slack for the altddrio most probably because of the center aligned set_false_path. However I think it should be okay. If remove those set_false_path, able to see the setup and hold slack?


2.You can only set IOE in assignment editor check that document link https://www.intel.com/content/www/us/en/docs/programmable/683801/current/programmable-ioe-delay.html

You can set this value in the Intel® Quartus® Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor.


Thanks,

Regards,

Sheng