No Ring Oscillator Example seems to works for me (Quartus II 15.0)

Hi,

before trying to stop me from it. I know very well why I want ring oscillators and have used them in a competitor's FPGA already, where it was easier to introduce them.

Now I wanted to try Altera, specifically the Stratix IV GX on a Terasic DE4 board, but seem to not get it working.

I use vhdl generate statements to make more than 1000 of them, so either they get reduced to 1 and I can't find that in the Technology Map Viewer (is there some way to preserve some names and hierarchy?), or they get completely removed. However, most of the time I see the wanted design in RTL Viewer. So I disabled all kind of synthesis settings that could lead to merging, but that didn't change anything.

None of these examples worked for me:

- After fixing the syntactical problems in http://www.alterawiki.com/wiki/ring_oscillator they looked ok in RTL Viewer but seemed to be gone after. I did only try instances of the verilog source. Is there more to it, required from the constraints etc.? It didn't look like that for me, and I am especially not trusting that design much if it doesn't even synthesize to begin with.

- Trying from the snippet there, and adding syn_keep and/or keep didn't help: http://www.alteraforum.com/forum/showthread.php?t=42155

- Multiple things I found, like using LUT_INPUT and LUT_OUTPUT and experimented with all the attributes/constraints.

I checked numerous posts and there seem to be options of using LCELL combinations, or LUT_INPUT/LUT_OUTPUT, or it might even be possible to use wysiwyg.stratixiv_components.all.

Which of them is the most straightforward solution, and might some of them not even work for me (Stratix IV)?

Overall I'd prefer any LUT2 to 4 that are connected to itself as a RO, with one LUT-state being used to disable/enable the oscillation. My last try of that is shown below the text.

I did not yet try instantiating components from wysiwyg.stratixiv_components.all as I first need to find and read documentation how to do that to get what I want. Would that be the solution or am I wasting just more time with that?

Thanks for any help / hints.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
library altera;
use altera.altera_syn_attributes.all;
ENTITY LUT_for_RO IS
PORT (
    a : IN STD_LOGIC;
    b : IN STD_LOGIC;
    c : IN STD_LOGIC;
    d : IN STD_LOGIC;
    o : OUT STD_LOGIC);
END LUT_for_RO;
ARCHITECTURE arch OF LUT_for_RO IS
    SIGNAL as, bs, cs, ds, os: STD_LOGIC;
    COMPONENT LUT_INPUT
        PORT (a_in : IN STD_LOGIC;
        a_out: OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT LUT_OUTPUT
        PORT (a_in : IN STD_LOGIC;
        a_out : OUT STD_LOGIC);
    END COMPONENT;
    
    attribute keep : boolean;
    attribute preserve : boolean;
    --attribute syn_keep : string;
    
    attribute keep of as : signal is true;
    attribute keep of bs : signal is true;
    attribute keep of cs : signal is true;
    attribute keep of ds : signal is true;
    attribute keep of os : signal is true;
    
    attribute preserve of as : signal is true;
    attribute preserve of bs : signal is true;
    attribute preserve of cs : signal is true;
    attribute preserve of ds : signal is true;
    attribute preserve of os : signal is true;
BEGIN
    LUT_a : LUT_INPUT
    PORT MAP (
    a_in => a,
    a_out => as);
    
    LUT_b : LUT_INPUT
    PORT MAP (
    a_in => b,
    a_out => bs);
    
    LUT_c : LUT_INPUT
    PORT MAP (
    a_in => c,
    a_out => cs);
    
    LUT_d : LUT_INPUT
    PORT MAP (
    a_in => d,
    a_out => ds);
    
    os <= not as or not bs;
    
    LUT_o : LUT_OUTPUT
    PORT MAP (
    a_in => os,
    a_out => o);
END arch;