No Ring Oscillator Example seems to works for me (Quartus II 15.0)

The Verilog had some syntactical problems so I didn't trusted it very much and just tried it shortly (always_ff instead of always and i++ instead of i = i+1), after fixing them it didn't work...

And oops, sorry the code I posted was at some non functional intermediate state, believe me I also had it with feedback. I will correct the first post to the one I tried last.

//edit: OK, sorry, the code was actually correct after all, I externally then instantiated it this way:

activity_ROs : for i in 0 to amount-1 generate
    begin
        ro_inv: LUT_for_RO
         port map (a => self_s(i), b => enable_i, c => '0', d => '0', o => self_s(i));
    end generate;

Maybe the problem is the other parts of the design, so I overlooked it in Technology Viewer. But that would mean that at least all multiple instances get removed. How can I keep all my 1000s of ROs?

//edit2: Okay I have to apologize, I saw it was System Verilog after all. Let's see if this helps, hope I can also instantiate it in a VHDL design