No Ring Oscillator Example seems to works for me (Quartus II 15.0)

Why not use the example from ring oscillator? Just because it's Verilog? I'd just copy that and move on. : )

I don't see anywhere in your code where it actually loops back? I synthesized it in Quartus and it shows the same thing. The Technology Map View shows three LUTs, as, bs and os, which looks correct. (Note that the keep attribute tries to keep that point as the output of a LUT or Register, i.e. so it can be tapped by SignalTap or something like that. It is not a stand-alone LUT. So in this case the OR gate gets absorbed into the LUT feeding point os.