Honored ContributorHi all,
I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it with 50MHz clock and i see no output on both the output signals. Please see the files below for .bdf and modelsim screenshot. Please help me how to see the output and what changes i need to make. Thank you Ash
Honored Contributordo you think the input-clock is 50MHz?
Honored ContributorHi Ash,
Just to check with you if the pll_locked got asserted? Can you try to apply a reset to the PLL?Honored Contributoryea that's what i have designed in Mega wizard plug in manager. I have chosen 50MHz for the input clock
Honored ContributorHi akira,
yea that's what i have designed in Mega wizard plug in manager. I have chosen 50MHz for the input clock ThanksHonored ContributorHi tiny007,
I added a reset as per what you said. still the output remains the same Undefined. Is there somewhere i am going wrong?Honored ContributorHi amod,
Two things: you only show 5-6 ns on your waveforms, the PLL models, like real PLLs, take some time to initialize and sync before you get an output. 6ns is not nearly enough time. I forget how long this takes in simulation (I think it's a lot less than for the real devices) but give it a us or so before you give up. Second, it looks like the clock you're feeding it is NOT 50MHz, but 10GHz! The period shown is 0.1ns, check your clock generation. -FredHonored ContributorFredH is right. Where is your testbench? Post it here.
Honored ContributorHi FredH i have changed the clock period to 0.02 us and run the simulation for half a second. still my output remains the same. Please see the attachment.
Thanks AshHonored ContributorHi krasner,
Could you please explain me how to generate testbench ?Honored ContributorAre you getting any warning when you run modelsim? Perhaps a library is not set up. See this thread: http://www.alteraforum.com/forum/showthread.php?t=21634
