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Honored Contributor
Honored ContributorNo PLL output on modelsim
Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
Altera_ForumHonored Contributor
Honored ContributorHi amod,
Two things: you only show 5-6 ns on your waveforms, the PLL models, like real PLLs, take some time to initialize and sync before you get an output. 6ns is not nearly enough time. I forget how long this takes in simulation (I think it's a lot less than for the real devices) but give it a us or so before you give up. Second, it looks like the clock you're feeding it is NOT 50MHz, but 10GHz! The period shown is 0.1ns, check your clock generation. -Fred
