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Altera_Forum
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11 years ago

No PLL output on modelsim

Hi all, I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it w...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi FredH i have changed the clock period to 0.02 us and run the simulation for half a second. still my output remains the same. Please see the attachment.

Thanks

Ash