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FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

No hardware detected in beta bus analyzer

Dear community, I have a Terasic DE5-Net FPGA based on Stratix V FPGA. I would like to monitor the Avalon MM bus by mean of the Bus analyzer toolkit. I followed the guide of this link (https://fpgaw...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

Did you add the JTAG Debug Link component as mentioned in the Wiki?