no failure or wainings reports in QUARTUSII for an obvious syntax error

"assign" statements are for signals defined as "wire".

Singals defined as "reg" should be assinged in an "always" statement (or block).

@haoask07:

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actually ,i wanna know why the software QUARTUSii didn't have syntax error report after the complete compilation .Exactly i know the mistake then.

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it is difficult to understand what problem you are experiencing from your wording.

Please send two (shortened) verilog descriptions:

1) with the error message

2) without the error message

your are refering to.

sanmao:

i modified as " wire[15:0] mem [16:0];"when i saw the error report after verilog description of "reg [15:0] mem [16:0]; assign mem[0] = 16'd0000;",and kept "assign mem[0] = 16'd0000;",and also i know there is no this type of data definition for memory array with "wire[15:0] mem [16:0];",but QUARTUSII does not have any warnings or errors about this .

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I know there is no this type of data definition for memory array with "wire[15:0] mem [16:0];"

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It's legal Verilog syntax. Just have a look on the IEEE 1364 Verilog specification, paragraph 4.9 Arrays. It has this example:

wire  y; 8-bit-wide vector wire indexed from 0 to 7

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It's legal Verilog syntax. Just have a look on the IEEE 1364 Verilog specification, paragraph 4.9 Arrays. It has this example:

wire  y; 8-bit-wide vector wire indexed from 0 to 7

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So ,the document i referred to is half-baked.

and it has no other difference with reg[15:0]mem[16:0];except that it initialized by assign =...........,and reg[15:0]mem[16:0];should be initialized in always module word by word?yes?

And i think the two data types for defining the memory array,will be the same situation that using the LEs resource inside the p-chip .Is this a right point of view?

thanks everyone for help.