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Altera_Forum
Honored Contributor
15 years agosanmao:
i modified as " wire[15:0] mem [16:0];"when i saw the error report after verilog description of "reg [15:0] mem [16:0]; assign mem[0] = 16'd0000;",and kept "assign mem[0] = 16'd0000;",and also i know there is no this type of data definition for memory array with "wire[15:0] mem [16:0];",but QUARTUSII does not have any warnings or errors about this .