NIOSII Boot Configuration with EPCS and JTAG-SFL

Yes, setting the pins as regular I/O should solve your problems.

As for the .jic workflow with an .elf file, AFAIK the only tool that can generate a correct bitstream for an EPCS chip from the .elf file is the command line tool elf2flash (the one called automatically from the Nios Flash Programmer). Unfortunately this tools generates a .srec file, which the Nios flash programmer is quite happy with, but that the Quartus programmer doesn't understand. (why, Altera, why do you make our lives so complicated???). So you need to convert this .srec file to the .hex format to make the Quartus programmer happy. A tool such as srec_cat (http://srecord.sourceforge.net/) can do that directly, or you can do as laland suggests and convert it to a binary format first and then to .hex

If you are using graphical tools from Eclipse I think the easiest workflow is the Nios flash programmer.

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Also you need to make these pins as user IO's in Device settings (Dual purpose pins, set as reular I/Os). See ug_embedded_ip, page 53.

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Ok thanks, i overlooked this point. Now i can set the epcs signals manually. I did it and recompile the fpga design, regenerate the bsp and rebuild the software. When i start the flash programmer it is still not successfull and the epcs clock line still shows no activity.

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Yes, setting the pins as regular I/O should solve your problems.

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Unfortunately it does not.

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But I tried a different appoach of converting the sof and elf files to *.flash, again to *.bin, combine both and then covert to *.hex. Now use the Quartus programmer to convert the file to jic file to program EPCS16. This is a long process but it worked for me. Used NIOS command line for file conversion.

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What exactly is the bin file format and how is it created from a flash format? There is a tool flash2dat, but no tools like dat2hex or bin2hex? What do you use to convert these formats.

I also found a tool elf2hex. But i am confused about settin as start- and end-adresses. Do I neet to set the ram adresses, the epcs controller adresses, or anything else?

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A tool such as srec_cat (http://srecord.sourceforge.net/) can do that directly, ...

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Here i'm working under windows. For development tasks i still installed cygwin. SRecord is not in the cygwin package repositorys. A first "./configure" shows that installing it manully is a complete new challenge.

Are you sure that the EPCS is working properly? You can use the Quartus programmer, upload an SFL image (you should find as ready compiled one as C:\altera\xx.x\quartus\common\devinfo\programmer\sfl_fpga_name.sof) and then do a new autodetect. Then it should show you the EPCS connected to the FPGA. Using a scope you should see the EPCS lines toggling and use it as a reference. Once you have that working you know that the communication between the EPCS and the FPGA is working properly and can focus on the Nios II flash programmer.

The only two explanations I can think of for your problem would be wrong pin assignment (chip select instead of clock, for example) or wrong EPCS controller address. As long as you are sure that the image in the FPGA matches the .sopcinfo file that the Nios Flash programmer uses (which it should, now that you have enabled the system ID check) you should have the correct EPCS controller address so I don't understant why the EPCS lines aren't even toggling.

As for SRecord, it looks like the author is rather stubborn about a Windows version... He doesn't even want to host a ready compiled version made by someone else... But there is a page explaining how to compile it, it looks like there are two dependencies to install: boost and libgcrypt: http://srecord.sourceforge.net/windows.html

You can't use elf2hex because it is only meant to be used for parallel memories directly connected to the CPU's masters. For the EPCS your first mandatory step is elf2flash, to convert your .elf application to a format understood by the EPCS bootloader. But except elf2flash I don't use Altera's flash conversion utilities any more. I find SRecord a lot more versatile, and it has cool features such as automatic checksum generation.

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Are you sure that the EPCS is working properly?

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Yes, before using NIOSII i set up a simple fpga configuration which flashes some LEDs. I wrote the design to the EPCS device and repower the fpga. The design was loaded from the epcs and the LEDs where flashing.

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You can use the Quartus programmer, upload an SFL image (you should find as ready compiled one as C:\altera\xx.x\quartus\common\devinfo\programmer\sfl_fpga_name.sof) and then do a new autodetect. Then it should show you the EPCS connected to the FPGA. Using a scope you should see the EPCS lines toggling and use it as a reference.

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Ok I've done this and it works. The EPCS16 device was detected properly and the epcs clock line has activity.

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Once you have that working you know that the communication between the EPCS and the FPGA is working properly and can focus on the Nios II flash programmer.

The only two explanations I can think of for your problem would be wrong pin assignment (chip select instead of clock, for example)

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I checked the pin assignement against the schematic of the board and against "Pin Information for the Cyclone ® III EP3C16 Device Version 1.3". It seems to be Okay.

• dclk -> K2 (DCLK)

• sdo -> D1 (DATA1, ASDO)

• data0 -> K1 (DATA0)

• sce -> E2 (FLASH_nCE, nCSO)

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[...] or wrong EPCS controller address. As long as you are sure that the image in the FPGA matches the .sopcinfo file that the Nios Flash programmer uses (which it should, now that you have enabled the system ID check) you should have the correct EPCS controller address so I don't understant why the EPCS lines aren't even toggling.

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In Qsys the mapping of the epcs controller is 0x21800-0x21fff. This seems to be the same for the flash-programmer.

Maybe i use the flash-rpgrammer incorrect. Here is my workflow:

[list]

[*]at first i use the quartus programmer to erase the EPCS device

[*]now i load the fpga configuration (*.sof file) with the quartus programmer via jtag into the fpga

[*]i choose "Run As -> NIOSII Hardware" from the Eclipse project menu

[*]now the system is running in the fpga (not written in the epcs -> volatile)

[*]i click "Terminate and Remove Launch" in the NIOSII console window to release the USB Blaster

[*]i choose "NIOS II -> Flash Programmer" from the Eclipse project menu

[*]after selecting "File -> New" i select hte *.sopcinfo file

[*]i add the *.sof file

[*]i add the *.elf file

[*]i cklick start

[/list]

There was no activity at the clock lines. I noticed, that the system on the fpga was stopped.

This is the output of the flash programmer:

Info: 23.04.2013 15:04:07 - (FEIN) sof2flash: Starting
Info: Info: *******************************************************************
Info: Info: Running Quartus II 32-bit Convert_programming_file
Info: Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.opt Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/NIOS_SYSTEM.sof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof
Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings
Info:     Info: Peak virtual memory: 126 megabytes
Info:     Info: Processing ended: Tue Apr 23 15:04:16 2013
Info:     Info: Elapsed time: 00:00:09
Info:     Info: Total CPU time (on all processors): 00:00:02
Info: Info: *******************************************************************
Info: Info: Running Quartus II 32-bit Convert_programming_file
Info: Info: Command: quartus_cpf --no_banner --convert Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.pof Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.rpd
Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings
Info:     Info: Peak virtual memory: 126 megabytes
Info:     Info: Processing ended: Tue Apr 23 15:04:31 2013
Info:     Info: Elapsed time: 00:00:15
Info:     Info: Total CPU time (on all processors): 00:00:02
Info: 23.04.2013 15:04:33 - (FEIN) sof2flash: Done
Info: Using cable "USB-Blaster ", device 1, instance 0x00
Info: Resetting and pausing target processor: OK
Info: Reading System ID at address 0x00022080: verified
Info: Processor data bus width is 32 bits
Info: Looking for EPCS registers at address 0x00021800 (with 32bit alignment)
Info:   Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Info:   Not here: reserved fields are non-zero
Info: Looking for EPCS registers at address 0x00021900 (with 32bit alignment)
Info:   Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C
Info:   Not here: reserved fields are non-zero
Info: Looking for EPCS registers at address 0x00021A00 (with 32bit alignment)
Info:   Initial values: 108001C4 1004D0FA 002EE03A 003F9C06 002EE03A 003F9506
Info:   Not here: reserved fields are non-zero
Info: Looking for EPCS registers at address 0x00021B00 (with 32bit alignment)
Info:   Initial values: 00000000 00000000 00000000 00000000 00000000 00000000
Info:   Not here: SPI_SLAVE_SEL has 0 valid bits (should be between 1 and 16)
Info: Looking for EPCS registers at address 0x00021C00 (with 32bit alignment)
Info:   Initial values: 00000014 00000014 00000260 00000000 00000014 00000001
Info:   Not here: reserved fields are non-zero
Info: No EPCS registers found: tried looking at addresses
Info:      0x00021800, 0x00021900, 0x00021A00, 0x00021B00 and 0x00021C00
Info: Leaving target processor paused
Error: Error code: 8 for command: $SOPC_KIT_NIOS2/bin/nios2-flash-programmer "Y:/TLK2711-SP/Terasic_DE0/NIOS_SYSTEM/flash/NIOS_SYSTEM_epcs.flash" --base=0x21800 --epcs --sidp=0x22080 --id=0x16 --timestamp=1366718316 --device=1 --instance=0 '--cable=USB-Blaster on localhost ' --program --verbose 

Hi

Commands to generate the hex file are given below.

sof2flash --epcs --compress --input=VHDL.sof --output=firmware.flash

elf2flash --epcs --after=firmware.flash --input=nios.elf --output=software.flash

nios2-elf-objcopy -I srec -O binary firmware.flash firmware.bin

nios2-elf-objcopy -I srec -O binary software.flash software.bin

cat firmware.bin software.bin > app_image.bin

nios2-elf-objcopy -I binary -O ihex app_image.bin app_image.hex

UsecQuartus pogrammer to convert this hex file to jic and program the board.

Using the above procedure, I am able to program the board and FPGA configures properly.

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elf2flash --epcs --after=firmware.flash --input=nios.elf --output=software.flash

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Hi laland. This program wants base adress and end adress specified. I can't find out what adresses are meant. Trying the ram and the epcs controller adress space does not work. I wonder what adresses are meant.

The help of elf2flash says this are the adresses of the flash. But the epcs flash device is not mapped directly to the processor. The epcs controller is mapped from 0x21820 to 0x21fff. This is a adress space ok about 1,9kiB.

My EPCS16 has 16Mbit ~ 1,9MiB of space.

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Daixiwen: Are you sure that the EPCS is working properly?

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Meanwhile i wrote a little program that writes "hello world" to a space in the EPC device by using the HAL driver of the epcs controller. After repowering the fpga and configure it again i can read the hello world string from the EPCS device.

At reading and writing i can trigger activitiy at the clock signal of the epcs device. So the connection / pin planning and the proper function of the epcs device is approved.

(Using the flash programmer does still not work).

Hi,

I used this command as it is, without specifying the start and end address of EPCS16.

I picked up those commands from another thread here on this forum.

Do you get error when you execute that command?

You are right that EPCS address is not directly mapped to processor.So end address is not known.

Okay, my fault. There was a typo on the command line. I can generate the hex file and write it into the EPCS device. Thank you for your suggestions.

After repowering the fpga nothing happens, the system does not start. If i reset the nios2 processor (with a button on the board) I can see activity on the epcs clock line. It seems that the nios2 loads the software after a reset. But the software does not run.

Only if I open the nios2-terminal, to have a look at the JTAG UART module, the system starts.

Is there a hidden handbrake anywhere which i have to respect?

Yes the elf2flash shouldn't ask for start or end addresses when you are using the --epcs and --after options, it will automatically put the data after the FPGA image.

Which embedded OS are you using, if any? Are you using the reduced drivers or the full ones? I know that some versions of the JTAG UART driver will block any writing transaction until a USB blaster is connected (it is the case with the eCos driver, for example, but IIRC the full version from the Altera HAL or with uC OS doesn't have this problem).

If in doubt you can have a look at the driver source code, it isn't that complicated.

As for your problem with the Nios flash programmer, I'm out of ideas. It looks like it doesn't find the SPI master at the expected address. It should fail on the first set of addresses, but should find it 1kbyte after the base address. As an example, here is a read operation done on a board with a Cyclone III and an EPCS64:

$ nios2-flash-programmer -c 3 -b 0x03400800 --epcs -R dump.flash --debug
Using cable "USB-Blaster on 192.168.0.74 ", device 1, instance 0x00
Resetting and pausing target processor: OK
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x03400800 (with 32bit alignment)
  Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
  Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x03400900 (with 32bit alignment)
  Initial values: 92400237 4A40100C 483FFD26 90000135 92400237 4A40200C
  Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x03400A00 (with 32bit alignment)
  Initial values: 108001C4 1004D0FA 002EE03A 003F9C06 002EE03A 003F9506
  Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x03400B00 (with 32bit alignment)
  Initial values: 00000000 00000000 00000000 00000000 00000000 00000000
  Not here: SPI_SLAVE_SEL has 0 valid bits (should be between 1 and 16)
Looking for EPCS registers at address 0x03400C00 (with 32bit alignment)
  Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
  Valid registers found
EPCS signature is 0x16
EPCS identifier is 0x202017
Using EPCS size information from section 
Device size is 8MByte (64Mbit)
Erase regions are:
  offset  0: 128 x 64K
EPCS status is 0x00
Read 8192KB in 70.8s (115.7KB/s)
Writing EPCS contents to dump.flash
Leaving target processor paused

Your workflow seems correct to. You could try and run the flash programmer right after you put the .sof flash, without running the embedded software first. Maybe the embedded software screws up the EPCS controller...

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Which embedded OS are you using, if any? Are you using the reduced drivers or the full ones? I know that some versions of the JTAG UART driver will block any writing transaction until a USB blaster is connected (it is the case with the eCos driver, for example, but IIRC the full version from the Altera HAL or with uC OS doesn't have this problem).

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Until now I don't use any OS, only the HAL. Deactivating the UART-JTAG driver solves the problem, now the system starts up after reset (without nios2-terminal).

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As for your problem with the Nios flash programmer, I'm out of ideas. It looks like it doesn't find the SPI master at the expected address. It should fail on the first set of addresses, but should find it 1kbyte after the base address. As an example, here is a read operation done on a board with a Cyclone III and an EPCS64: [...]

Your workflow seems correct to. You could try and run the flash programmer right after you put the .sof flash, without running the embedded software first. Maybe the embedded software screws up the EPCS controller...

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The reading of the EPCS registers somtimes fails at the first register and sometimes at a higher register. Running the flash programmer right after putting the sof file to the fpga does also not work. I don't waste any more time with the flash programmer and use the workflow described by laland.

In any case, using command line tools is more favour to me. I will try to do my builds etc. per command line. Eclipse is uncomfortable slow, but for the first steps it was useful.

I think my Problem is solved and i can program my software to a epcs device.

Much thanks to Daixiwn and laland, you helped me alot!

best regards,

lodentoni