NIOSII Boot Configuration with EPCS and JTAG-SFL

Are you sure that the EPCS is working properly? You can use the Quartus programmer, upload an SFL image (you should find as ready compiled one as C:\altera\xx.x\quartus\common\devinfo\programmer\sfl_fpga_name.sof) and then do a new autodetect. Then it should show you the EPCS connected to the FPGA. Using a scope you should see the EPCS lines toggling and use it as a reference. Once you have that working you know that the communication between the EPCS and the FPGA is working properly and can focus on the Nios II flash programmer.

The only two explanations I can think of for your problem would be wrong pin assignment (chip select instead of clock, for example) or wrong EPCS controller address. As long as you are sure that the image in the FPGA matches the .sopcinfo file that the Nios Flash programmer uses (which it should, now that you have enabled the system ID check) you should have the correct EPCS controller address so I don't understant why the EPCS lines aren't even toggling.

As for SRecord, it looks like the author is rather stubborn about a Windows version... He doesn't even want to host a ready compiled version made by someone else... But there is a page explaining how to compile it, it looks like there are two dependencies to install: boost and libgcrypt: http://srecord.sourceforge.net/windows.html

You can't use elf2hex because it is only meant to be used for parallel memories directly connected to the CPU's masters. For the EPCS your first mandatory step is elf2flash, to convert your .elf application to a format understood by the EPCS bootloader. But except elf2flash I don't use Altera's flash conversion utilities any more. I find SRecord a lot more versatile, and it has cool features such as automatic checksum generation.