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Altera_Forum
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12 years ago

NIOSII Boot Configuration with EPCS and JTAG-SFL

Hello,

i have a problem with configuring and booting my system from an epcs device. The topic is more about the correct design-flow, so i think this should be the right sub-fourm.

the test-system

The hardware i am experimenting on is a DE0 board from Terasic. It has a EP3C16 FPGA with an EPCS16 Flash connected.

I generated an QSYS design with Clock Source, NiosIIe, On-Chip RAM, RS232 UART, System ID, Timer, JTAG UART, Parallel I/O, and EPCS Serial Flash Controller.

The reset vector is set to the EPCS controller, the exception vector is set to the ram.

The software consists of a RS232 console that controls on-board LEDs with the parallel I/O.

what does work

I can configure the FPGA via JTAG or via AS (after programming the EPCS device via JTAG SFL), both works well. This means only FPGA configuration, no software loading.

In Eclipse i can download the software via JTAG and run it. Principally all works.

what does not work

The next step i want to learn is how to load software from the epcs device. I am still working for some days and it does not work.

workflow

I build the software in eclipse and use "make mem_init_generate" to build a hex-file from the elf-file.

In Quartus i try to read the hex-file within the "Convert Programming File" - dialog.

The generation of the JTAG Indirect Configuration File fails with the message "Data in HEX File overlaps between data blocks at address 8 and address 0".

Here i found a description of a nearly similar problem: .altera.com/support/kdb/solutions/rd09282011_907.html

But the solution does not work, maybe because its Quatrus 11.0 and i am using 12.0.

my question

Can anyone tell me a workflow for programming FPGA configuration data and software into a EPCS device via JTAG SFL?

best regards,

lodentoni

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