NIOSII Boot Configuration with EPCS and JTAG-SFL

You basically have 3 ways to program an EPCS chip:[list][*]connect the EPCS directly to the USB blaster. This requires an additional connector on your board, different from the JTAG one[*]Generate a .jic file containing everything you need and use the Quartus programmer to program the EPCS through JTAG. The programmer will upload an SFL image to the FPGA, and this SFL image will connect the EPCS pins to a virtual JTAG component that the Quartus programmer can then access to programm the EPCS[*]Use the Nios II Flash programmer. This programmer also uses JTAG, but instead of an SFL image, needs an FPGA image with a Nios II CPU. Then it will use the JTAG module inside the Nios CPU to access the EPCS controller component inside the FPGA, and that way access the EPCS.[/list]You are currently using method 3, and that is why it requires an FPGA image with a Nios CPU and an EPCS controller. It also needs the *right* FPGA image to be there, because it needs to know what address to use to access the EPCS controller.

As for your current error, I agree with laland. It looks like it nos finds the EPCS controller, but somehow doesn't manage to communicate with the EPCS chip itself. Check that the EPCS controller ports are connected to the right FPGA pins, and if possible check with a scope the signals between the FPGA and the EPCS chip to see if anything is happening there when you try to program the flash.