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[list][*]Generate a .jic file containing everything you need and use the Quartus programmer to program the EPCS through JTAG. The programmer will upload an SFL image to the FPGA, and this SFL image will connect the EPCS pins to a virtual JTAG component that the Quartus programmer can then access to programm the EPCS[/list]
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This was my preferred solution. But as described in my earlier posts, no of the workflows i read and try were successful. It fail to generate the jic file with fpga configuration and software image.
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[list][*]Use the Nios II Flash programmer. This programmer also uses JTAG, but instead of an SFL image, needs an FPGA image with a Nios II CPU. Then it will use the JTAG module inside the Nios CPU to access the EPCS controller component inside the FPGA, and that way access the EPCS.[/list]
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This is complete new to me. I thought the flash programmer uses also a kind of SFL design to write to the epcs flash. Anyway, i tried to configure the fpga via jtag and then to use the flash programmer, wich was not successful.
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It looks like it nos finds the EPCS controller, but somehow doesn't manage to communicate with the EPCS chip itself. Check that the EPCS controller ports are connected to the right FPGA pins, and if possible check with a scope the signals between the FPGA and the EPCS chip to see if anything is happening there when you try to program the flash.
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I checked the clock signlas of the epcs device. There is no activity while using the flash programmer.
In the Embedded Peripherals IP User Guide i read, the connections for the EPCS Controller where automatically generated. But there are some exceptions to Cyclone III devices. So i try to uncheck the automatic detection of connections in the EPCS Controller MegaWizard and place the connections manually. But then the fitter brings an error message because of placing two signals to one pin (the manually placed epcs controller signals and automatically generated signals "~ALTERA_*").
Do anyone know how how the EPCS Controller is correctly implemented in Cyclone III designs? In the Embedded Peripherals IP Guide is written that something is to respect with cyclone III devices but i can't find a manual in which is written what exactly is to do.
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