Forum Discussion
Asifa
New Contributor
New ContributorNIOS ii/e clock frequency differ from real-time running frequency.
I have created a Qsys circuit using Nios II/e, with a clock frequency of 50 MHz. Other peripherals are also connected, as shown in the attached photo. I wrote a program in Eclipse, and when I checked...
sstrell
Super Contributor
Super ContributorThat's great but you still haven't explained how you are providing the 50MHz clock to the design in hardware or the code that you are using to help understand why this might be a software issue instead of a hardware issue. Just saying in Platform Designer "I'm using a 50 MHz clock" doesn't make it happen unless you are actually providing that in hardware.
AsifaNew Contributor
New ContributorI am only working with GPIO pins; I have not attached any extra hardware to the FPGA (Cyclone V). Sorry, I am not getting your point. How do I provide a clock source on the hardware (FPGA)? I have also attached a part of the code to check if it’s a coding problem.
