I have got this problem when I synthesize my design on Quartus II but when I use xilinx software its work perfectly the error is that " left bound of the range must be a constant " and it's indicated to this line ----------------------------------------------- Reg_Q:process (CLK, r_by_2) begin if (CLK'event and CLK='1') then if RESET='1' then q<= (others => '0'); else case CS is ----------------------------------- when S2 => q<=p; ----------------------------------- when S4 => if(r_by_2 = 1) then q <= q (m_size-r_by_2-1 downto 0) & q(m_size-1); else ---------->>>>> q(m_size-1 downto r_by_2) <= q (m_size - r_by_2 - 1 downto 0); q(r_by_2-1 downto 0) <= q(m_size-1 downto m_size - r_by_2); end if; ----------------------------------- when others => null; ----------------------------------- end case; end if; end if; end process; ----------------------------------------------- here is the signal definition signal p, q, t : std_logic_vector (m_size-1 downto 0); -- Does anyone have idea how to make this synthesizable? Im making a normal basis multiplier thank you

what is the size of r_by_2? if its not a constant, how do you know that both vector sizes are the same? You could just stick it in a for loop and do it bit by bit. for i in 0 to r_by_2-1 loop q(i) <= q(i+r_by_2); q(i+r_by_2) <= q(i); end loop;

the r_by_2 is r_by_2 : integer range 0 to m_size_1 I have tried the for loop but its give me another errors I didnt get it so can you explain more the problem is I'm modifying this code and trying to break it down into datapath and controller then Im going to write another code using different numbering system so I need to understand it perfectly

what dont you get? can you post more of your code?

here is more of my code Reg_P:process (CLK) begin if (CLK'event and CLK='1') then if RESET='1' then p<= (others => '0'); else case CS is ----------------------------------- when S1 => p <= X_in; ----------------------------------- when S7 => if (mul_result = '1') then p <= mul_c; end if; ----------------------------------- when S8 => p <= t; ----------------------------------- when S10 => p <= p(m_size-2 downto 0) & p(m_size-1); ----------------------------------- when others => null; ----------------------------------- end case; end if; end if; end process; ----------------------------------------------- Reg_Q:process (CLK, r_by_2) begin if (CLK'event and CLK='1') then if RESET='1' then q<= (others => '0'); else case CS is ----------------------------------- when S2 => q<=p; ----------------------------------- when S4 => if(r_by_2 = 1) then q <= q (m_size-r_by_2-1 downto 0) & q(m_size-1); else q(m_size-1 downto r_by_2) <= q (m_size - r_by_2 - 1 downto 0); q(r_by_2-1 downto 0) <= q(m_size-1 downto m_size - r_by_2); end if; ----------------------------------- when others => null; ----------------------------------- end case; end if; end if; end process;

when S4 => if(r_by_2 = 1) then q <= q (m_size-r_by_2-1 downto 0) & q(m_size-1); else for i in 0 to r_by_2-1 loop q(i) <= q(i+r_by_2); q(i+r_by_2) <= q(i); end loop; end if;

Altera_Forum

Honored Contributor

14 years ago

need a help with strange error" left bound of the range must be a constant "

I have got this problem when I synthesize my design on Quartus II but when I use xilinx software its work perfectly

the error is that " left bound of the range must be a constant "

and it's indicated to this line

-----------------------------------------------

Reg_Q:process (CLK, r_by_2)

begin

if (CLK'event and CLK='1') then

if RESET='1' then

q<= (others => '0');

else

case CS is

-----------------------------------

when S2 =>

q<=p;

-----------------------------------

when S4 =>

if(r_by_2 = 1) then

q <= q (m_size-r_by_2-1 downto 0) & q(m_size-1);

else

---------->>>>> q(m_size-1 downto r_by_2) <= q (m_size - r_by_2 - 1 downto 0);

q(r_by_2-1 downto 0) <= q(m_size-1 downto m_size - r_by_2);

end if;

-----------------------------------

when others =>

null;

-----------------------------------

end case;

end if;

end process;

-----------------------------------------------

here is the signal definition

signal p, q, t : std_logic_vector (m_size-1 downto 0); --

Does anyone have idea how to make this synthesizable?

Im making a normal basis multiplier

thank you

library ieee; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use ieee.math_real.all ; entity ahl2006 is generic ( MSIZE : natural := 16 ; SHIFT_DIRECTION : string := "RIGHT" ) ; port ( Clk : in std_logic ; Reset : in std_logic ; Ld : in std_logic ; Shift : in std_logic ; D : in std_logic_vector(MSIZE - 1 downto 0 ) ; Sel : in natural range 0 to MSIZE - 1 ; Q : out std_logic_vector(MSIZE - 1 downto 0 ) ) ; end ahl2006 ; architecture a of ahl2006 is constant MSIZE_IS_POWER_OF_2 : boolean := (2 ** floor( log2( real( MSIZE ))) = real( MSIZE ) ) ; constant MWIDTH : natural := integer( floor( log2( real( MSIZE )))) ; signal lq : std_logic_vector(MSIZE - 1 downto 0 ) ; begin process( Reset , Clk ) begin if (Reset = '1') then lq <= (others => '0') ; elsif rising_edge( Clk ) then if (Ld = '1') then lq <= D ; elsif (Shift = '1') then if SHIFT_DIRECTION = "LEFT" then for i in MSIZE - 1 downto 0 loop if MSIZE_IS_POWER_OF_2 then lq(i) <= lq( (MSIZE + i - Sel) mod MSIZE ) ; else if (i >= Sel) then lq(i) <= lq(i - Sel) ; else lq(i) <= lq( MSIZE + i - Sel) ; end if ; end if ; end loop ; else for i in 0 to MSIZE - 1 loop if MSIZE_IS_POWER_OF_2 then lq(i) <= lq((i + Sel) mod MSIZE) ; else if (i + Sel) < MSIZE then lq(i) <= lq(i + Sel) ; else lq(i) <= lq(i + Sel - MSIZE) ; end if ; end if ; end loop ; end if ; end if ; end if ; end process ; Q <= lq ; end a ;

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need a help with strange error" left bound of the range must be a constant "

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