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Altera_Forum
Honored Contributor
14 years agoLooking a bit deeper, I realised that I gave you a solution for a 'right' rotate where your code shows a 'left' rotate. So I experimented a bit with my code, and at the same time getting to know some of ModelSim quirks (as sometimes QII synthesizes OK, but Modelsim stops on a negative value for a natural etc.)
Here is my complete test code:library ieee;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
entity ahl2006 is
generic (
MSIZE : natural := 16 ;
SHIFT_DIRECTION : string := "RIGHT"
) ;
port (
Clk : in std_logic ;
Reset : in std_logic ;
Ld : in std_logic ;
Shift : in std_logic ;
D : in std_logic_vector(MSIZE - 1 downto 0 ) ;
Sel : in natural range 0 to MSIZE - 1 ;
Q : out std_logic_vector(MSIZE - 1 downto 0 )
) ;
end ahl2006 ;
architecture a of ahl2006 is
constant MSIZE_IS_POWER_OF_2 : boolean := (2 ** floor( log2( real( MSIZE ))) = real( MSIZE ) ) ;
constant MWIDTH : natural := integer( floor( log2( real( MSIZE )))) ;
signal lq : std_logic_vector(MSIZE - 1 downto 0 ) ;
begin
process( Reset , Clk )
begin
if (Reset = '1') then
lq <= (others => '0') ;
elsif rising_edge( Clk ) then
if (Ld = '1') then
lq <= D ;
elsif (Shift = '1') then
if SHIFT_DIRECTION = "LEFT" then
for i in MSIZE - 1 downto 0 loop
if MSIZE_IS_POWER_OF_2 then
lq(i) <= lq( (MSIZE + i - Sel) mod MSIZE ) ;
else
if (i >= Sel) then
lq(i) <= lq(i - Sel) ;
else
lq(i) <= lq( MSIZE + i - Sel) ;
end if ;
end if ;
end loop ;
else
for i in 0 to MSIZE - 1 loop
if MSIZE_IS_POWER_OF_2 then
lq(i) <= lq((i + Sel) mod MSIZE) ;
else
if (i + Sel) < MSIZE then
lq(i) <= lq(i + Sel) ;
else
lq(i) <= lq(i + Sel - MSIZE) ;
end if ;
end if ;
end loop ;
end if ;
end if ;
end if ;
end process ;
Q <= lq ;
end a ;
Today I also ran an RTL-siulation for MSIZE = 16, for both LEFT and RIGHT rotates to verify proper operation.