Native Phy Transceiver rx_cdr_refclk from PLL

i get the following fitting error:

Error (11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" cannot connect to PLD port "OUTCLK[0]" of "IOPLL" for atom "crm:crm_inst|pll_311_622:pll_311_622_dn_sfp_based_clks|pll_311_622_altera_iopll_161_dytpzvi:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst".

Extra Info (13133): Output port's "OUTCLK[0]" atom name is "crm:crm_inst|pll_311_622:pll_311_622_dn_sfp_based_clks|pll_311_622_altera_iopll_161_dytpzvi:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst".

Extra Info (13134): Input port's "REF_IQCLK[0]" atom name is "native_phy_trans_duplex:up_native_phy_trans_duplex_inst|native_phy_trans_duplex_altera_xcvr_native_a10_161_b2nqdiy:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm4:inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux".

Extra Info (12879): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" can connect to:

Extra Info (12880): Port "O_REFCLK_A[0]" of "HSSI_REFCLK_DIVIDER"

please advice,

thanks,

Oren

Hi,

As I understand it, you observe some issue when trying to use IO PLL to drive the CDR refclk of Native PHY in A10 devices. For your information, as I check with the A10 XCVR PHY user guide, seems like it does not list out PLL as a refclk source to the XCVR. Just to add on that generally it is recommended to use dedicated refclk for optimal performance.

As a workaround, you may try one of the following to see if they will work:

1. Instead of using IOPLL, try to use fPLL to drive the CDR refclk to see if it work.

2. Route the PLL output clock to Global Clock network and then connect back to the CDR refclk. You may use ALTCLKCTRL to force the PLL output clock to GCLK to see if it work.

If none of the above is working, you might need to sending the PLL output clock to output pin, go through clock cleaner and then loop back to CDR refclk.

Thank you.

Chee Pin

Hi,

Thanks a lot.

As i am looking for optimal performances i will send the PLL output clock and loop it back to CDR refclk.

Oren

Hi,

is this some kind of IP? should i use it in the design before sending it out? i know there are HW modules that clean the Jitter.

Oren

ok,

thanks a lot.

Oren