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OLevy1's avatar
OLevy1
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7 years ago

Native Phy Transceiver rx_cdr_refclk from PLL

hi, in one of me designs i would like to use 2 Native Phy Transceivers to receive 2 different serial information. one of the Native Phy Transceivers rx_ref_clk is from a dedicated pin BUT the other...
OLevy1's avatar
OLevy1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

i get the following fitting error:

Error (11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" cannot connect to PLD port "OUTCLK[0]" of "IOPLL" for atom "crm:crm_inst|pll_311_622:pll_311_622_dn_sfp_based_clks|pll_311_622_altera_iopll_161_dytpzvi:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst".

Extra Info (13133): Output port's "OUTCLK[0]" atom name is "crm:crm_inst|pll_311_622:pll_311_622_dn_sfp_based_clks|pll_311_622_altera_iopll_161_dytpzvi:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst".

Extra Info (13134): Input port's "REF_IQCLK[0]" atom name is "native_phy_trans_duplex:up_native_phy_trans_duplex_inst|native_phy_trans_duplex_altera_xcvr_native_a10_161_b2nqdiy:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm4:inst_twentynm_pma|gen_twentynm_hssi_pma_cdr_refclk_select_mux.inst_twentynm_hssi_pma_cdr_refclk_select_mux".

Extra Info (12879): Input port "REF_IQCLK[0]" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" can connect to:

Extra Info (12880): Port "O_REFCLK_A[0]" of "HSSI_REFCLK_DIVIDER"

please advice,

thanks,

Oren