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I'm further confused again.. I now have a problem in my Top level module:
// Shared buses wire [15 : 0 ] dataBus; // Registers to be switched onto the bus logic [15 : 0 ] dataRAM; //bit[ 15:0 ] dataVal; logic[ 15:0 ] dataVal; // logic or bit? Made no difference .. assign dataBus = ( chipSelectRAM ) ? dataRAM : 16'bZZZZZZZZZZZZZZZZ; .. always_ff @( posedge clk ) .. dataVal = dataBus; // Error here
Error (13076): The node "dataVal" has multiple drivers due to the non-tri-state driver "SDRAMController8Bit:sdramController|ioData[8]"
dataBus is connected to sdramController's ioData wire
dataRAM was being used for outgoing data.
So I modified the code further, renaming dataRAM to dataOut and adding a dataIn and now it compiles:
logic [15 : 0 ] dataOut; logic [15 : 0 ] dataIn; assign dataBus = ( chipSelectRAM ) ? dataOut : 16'bZZZZZZZZZZZZZZZZ; // Do I need to include iSDRAMWriteRequest here?? assign dataIn = ( chipSelectRAM ) ? dataBus : 16'bZZZZZZZZZZZZZZZZ; // Do I need to include ~iSDRAMWriteRequest here??
Question: If using dataBus for incoming and outgoing data, do I always need to provide a separate register for incoming and outgoing as I have done above?
Hi,
This link explains the cause of Error (13076)
If it doesn't help, kindly share the design QAR for investigation. To create the QAR file, click on Project > Archive Project > Archive.
Thanks
Best regards,
KhaiY
- SparkyNZ5 years ago
Contributor
Hi @KhaiChein_Y_Intel . I've just shared my project with @KennyTan_Altera on my other post about the "due to conflicting nodes" error. It may be easier to see where I'm completely going wrong with that.. and perhaps you guys can work together so you don't solve the same problem twice. Sorry about that.
See here: